Many high speed serial communication systems only transmit data over the communication media. In other words, these systems do not transmit clock signals that may be used by a receiver to recover data from the data stream in the signal received via the communication media. Consequently, receivers for high speed serial communication systems typically include clock and data recovery circuits that produce a clock signal synchronized with the incoming data stream that is then used to recover the data from the data stream. Data is typically recovered by generating a clock signal at a frequency that matches the frequency of the data stream. The clock is then used to sample or recover the individual data bits from the incoming data stream.
Some conventional receivers utilize a clock and data recovery circuit and retimer to recover data from a received signal in the above described manner. Typically the received signal is amplified by one or more buffer stages and the clock and data recovery circuit generates an extracted clock signal that has a phase and/or frequency that is fixed relative to the phase and/or frequency of the data stream in the received amplified signal. Using this recovered clock, the retimer extracts the data from the received signal.
Typically, the system is designed so that the retimer extracts the data from approximately the middle of each data symbol in the data stream. The retimer may comprise, by way of example, an edge-triggered flip flop that latches the received signal on an edge (e.g., the falling edge) of the clock. In this case, the clock and data recovery circuit is designed to align the edges of the extracted clock (in this example the rising edge) with the transition edge of the received data stream.
A typical clock and data recovery circuit uses a phase lock loop (PLL) or delay lock loop (DLL) to align the transition edges of the extracted clock with the transition edges of the incoming data stream. FIG. 1 is a simplified block diagram of one embodiment of a DLL 100.
The DLL 100 includes a phase detector 120 that receives, by way of example, a clock signal 110 on a first input and a feedback output signal 150(a) of the delay lock loop on a second input. Typically, the phase detector 120 generates at least one phase error signal 120(a) that is representative of the phase relationship between the feedback output signal 150(a) and the clock signal 110.
For example, the phase detector 120 may compare transitions in the clock 110 to the rising edges or the falling edges of the feedback output signal 150(a). The phase detector 120 then produces, by way of example, a phase error signal 120(a) that indicates whether the feedback output signal leads or lags the clock signal.
The phase error signal 120(a) drives a charge pump 130 that generates a current signal having a magnitude that varies in response to the phase error signal. A loop filter 140 then converts the current signal output by charge pump 130 to a voltage signal. This voltage signal drives a delay circuit (e.g., a variable delay line) 150 that is configured to delay a signal by an amount of time according to the magnitude of the applied voltage. In this way, the delay 150 may delay an input signal to generate an output signal 150(a) where the transition edges of the output signal 150(a) are aligned with the transition edges of the clock signal 110.
FIG. 2 illustrates an embodiment of a delay lock loop 200 that includes a phase detector 220, a digital filter 230 and a phase rotator 260. The phase detector 220 receives, by way of example, an incoming signal (e.g., a data signal) 210 on a first input and a feedback output signal 260(a) of the delay lock loop on a second input. Typically, the phase detector 220 generates at least one phase error signal 220(a) in accordance with the phase relationship between the feedback output signal 260(a) and the incoming data signal 210.
The phase error signal 220(a) drives a digital filter 230 that generates at least one digital control signal to control the phase rotation of a phase rotator 260. Thus, based on the digital control signal, the phase rotator 260 may shift the phase of a signal (e.g., a clock signal) 250 to generate an output signal 260(a) where the transition edges of the output signal 260(a) are aligned with the transition edges of the incoming data signal 210.
In some applications, the input signals of the phase detector will be of the same frequency. For these applications, the phase detector discussed above may consist of a phase and frequency detector (PFD). As illustrated in FIG. 3 one embodiment of a PFD 300 may include two flip flops 310(a–b) driven by first and second input signals 320 and 330, respectively, having the same frequency. In this embodiment AND gate 340 receives the output of each of the flip flops 310(a) and 310(b) and generates a common reset signal 370 for these flip flops.
When input signal 320 leads input signal 330 the up output signal 350 is high and the down output signal 360 is low. These phase error signals (when processed and fed to a delay component as discussed above for example) may, for example, cause a reduction in the delay imparted on the input signal 320. As a result, the transition edges of the delayed signal fed back to the input of the PFD will be more closely aligned with the transition edges of the other input signal 330.
When input signal 320 lags input signal 330 the up output signal 350 will be low and the down output signal 350 will be high. In this case, the delay imparted on the feedback signal (e.g., input 320) is increased to align the edges of the input signals 320 and 330.
For applications where the frequencies of the input signals to the phase detector are not equal, phase detection may be provided by, for example, a linear phase detector or a binary phase detector. In operation the output of a linear phase detector is proportional to the phase difference of its input signals.
The output of a binary phase detector on the other hand is one of two values (e.g., high or low), indicative of whether one signal leads or lags the other signal. Binary phase detectors do not, however, provide an indication of the magnitude of the phase difference between the signals.
FIG. 4 is a simplified block diagram of one embodiment of a binary phase detector 400 having three flip flips 410(a–c) each of which is driven by a first input signal 420 and a second input signal 430(a, b or c). Conventionally, the first input signal has a lower frequency than the second input signal of the phase detector. In the embodiment of FIG. 4 the second input signals 430(a–c) of the flips flops 410(a–c), respectively, are identical clock signals except that there is a 90 degree phase shift between successive signals. AND gates 440 and 450 compare the outputs of the flip flops 410(a–c) to generate an up signal (early) 460 and a down signal (late) 470, respectively, indicative of whether the first input signal 420 leads or lags the second input signal 430. The phase error signals 460 and 470 are then used to adjust the phase of an input signal, for example, as discussed above.
The flip flops 410(a–c) of the binary phase detector 400 operate at the speed of the frequency of the input clock signal 430 and are, therefore, the highest frequency components of the phase detector and the delay lock loop in this embodiment. Similarly, of the components in a conventional delay lock loop such as those illustrated in FIGS. 1 and 2, the phase detector typically operates at the highest frequency.
The input capacitance of a phase detector capable of operating at higher speeds typically presents a higher load to the input signal in comparison to a phase detector that operates at lower speeds. This additional load tends to adversely affect the performance and power consumption of the device.
To facilitate operation at high speeds, high speed CML flip flops implemented in CMOS logic for operation at or above 10 GHz may include inductive loads to tune out the parasitic capacitive loading on the inputs of the flip flop and to increase the bandwidth of the device. However, typical spiral inductors are relatively large devices that consume considerable die area. Thus, use of these inductors may increase the relative cost and size of the phase detector. In addition, high speed flip flops tend consume considerably more power than comparable devices operating at lower speeds.
In summary, a phase detector that operates at high speed may be difficult to design, may consume relatively large amounts of power, and may occupy a relatively large die area as compared to a phase detector that operates at lower speeds.